In a metal-oxide-semiconductor field-effect transistor (MOSFET), voltage is applied on the gate to control the current in a channel region to generate a switching signal (on-off). However, when semiconductor technology enters into a sub-45 nm node, the channel current control ability of traditional planar MOSFETs may become weak, thus a severe leakage current may be generated. Fin field-effect transistors (FinFET) are novel multiple-gate devices. A FinFET may include semiconductor fin structures protruding from the surface of a semiconductor substrate, a gate structure covering top and side surfaces of the fin structure, and source/drain regions in the fin structure at both sides of the gate structure.
In a gate-last process, a dummy gate may be formed first, followed by sequentially forming a sidewall spacer, source/drain regions, and an interlayer dielectric layer; then the dummy gate may be removed, and a gate structure may be formed. In the gate-last process for forming a FinFET, because fins may protrude from the surface of a semiconductor substrate, the surface of a dummy gate formed on the surface of the semiconductor substrate may be uneven. FIG. 1 illustrates a dummy gate structure of an existing fabrication process for forming a FinFET. The FinFET includes a semiconductor substrate 100; a plurality of protruding fins 101 on the semiconductor substrate 100; and a plurality of insulation structures 102 in between adjacent fins 101 covering a surface of the semiconductor substrate 100 and a portion of surfaces of the fins 101. A surface of the isolations structures 102 is lower than a surface of the fins 101. The FinFET also includes a dummy gate material layer 103 on the fins 101 and the isolation structures 102.
Referring FIG. 1, because the top surface of the isolation structures 102 is lower than the top surface of the fins 101, groves may be formed in between adjacent fins 101. After forming the dummy gate material layer 103, the groves are filled with the dummy gate material layer 103. The surface of a portion of the dummy gate material layer 103 on the isolation structures 102 is lower than the surface of a portion of the dummy gate material layer 103 on the fins. Thus, the surface of the dummy gate material layer 103 is uneven, which may affect subsequent processes.
In order to solve the uneven surface problem, a chemical mechanical polishing (CMP) process may be used to polish the surface of the dummy gate material layer 103. After the CMP process, the surface of the portion of the dummy gate material layer 103 on the isolation structure 102 may level with the surface of the portion of the dummy gate material layer 103 on the fins 101. However, there may be no polishing stop layer in the CMP process, the thickness of a remaining portion of the dummy gate material layer 103 after the CMP process may be difficult to control. Therefore, the thickness of the remaining dummy gate material layer may be uneven. The disclosed device structures, methods and systems are directed to solve one or more problems set forth above and other problems.